Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by specialized programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The data in a cell is determined by the presence or absence of the charge in the floating gate. The cells are usually grouped into sections called “erase blocks.” Each of the cells within an erase block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation.
Two common types of Flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form the basic memory cell configuration each is arranged in. In the NOR array architecture, the floating gate memory cells of the memory array are arranged in a matrix. The gates of each floating gate memory cell of the array matrix are coupled by rows to word select lines and their drains are coupled to column bit lines. The NOR architecture floating gate memory array is accessed by a row decoder activating a row of floating gate memory cells by selecting the word select line coupled to their gates. The row of selected memory cells then place their data values on the column bit lines by flowing a differing current if in a programmed state or not programmed state from a coupled source line to the coupled column bit lines.
A NAND array architecture also arranges its array of floating gate memory cells in a matrix such that the gates of each floating gate memory cell of the array are coupled by rows to word select lines. However each memory cell is not directly coupled to a column bit line by its drain. Instead, the memory cells of the array are arranged together in groups, typically of 16 each, where the memory cells coupled together in series, source to drain, between a source line and a column bit line. The NAND architecture floating gate memory array is then accessed by a row decoder activating a row of floating gate memory cells by selecting the word select line coupled to their gates. In addition, the word lines coupled to the gates the unselected memory cells of each group are driven to operate the unselected memory cells of each group as pass transistors, so that they pass current in a manner that is unrestricted by their stored data values. Current then flows from the source line to the column bit line through each series coupled group, restricted only by the selected memory cells of each group. Thereby placing the current encoded data values of the row of selected memory cells on the column bit lines.
Because all the cells in an erase block of a Flash memory device must be erased all at once, one cannot directly rewrite a Flash memory cell without first engaging in a block erase operation. Erase block management (EBM) provides an abstraction layer for this to the host, allowing the Flash device to appear as a freely rewrite-able device, including, but not limited to, managing the logical address to physical erase block translation mapping for reads and writes, the assignment of erased and available erase blocks for utilization, and the scheduling erase blocks that have been used and closed out for block erasure. Erase block management also allows for load leveling of the internal floating gate memory cells to help prevent write fatigue failure. Write fatigue is where the floating gate memory cell, after repetitive writes and erasures, no longer properly erases and removes charge from the floating gate.
Many modern Flash memories include special purpose “protection” registers. Protection registers are limited-size non-volatile storage areas (typically 128-bits) that are separate from the erase blocks of the Flash memory. Protection registers are typically utilized for storage of special purpose device identifiers and/or security codes that are associated with the Flash memory device and/or the data contents of its erase blocks. Once programmed, protection registers can be locked by the programming of “lock bits” that are associated with each individual protection register and/or protection register segment. With the lock bits set, the associated protection register or protection register segments are rendered unchangeable by the end-user of the device or system that incorporates the Flash memory. Lock bits are generally floating gate memory cells that have no erasure mechanism and thus cannot be erased once they are programmed. Lock bits can be incorporated into the protection register itself or can be standalone memory cells. If the Flash memory device notes that a lock bit protecting a protection register or a portion of a protection register is set, it disallows any attempts to manipulate or program the protection register or portion of protection register that is protected by the lock bit.
FIG. 1 shows a simplified diagram of a system incorporating a Flash memory 100 of the prior art coupled to a processing device or controller 102. In the system 128, the Flash memory 100 has an address interface 104, a control interface 106, and a data interface 108 that are each coupled to the processing device 102 to allow memory read and write accesses. Internal to the Flash memory device a control state machine 110 directs the internal operation; managing the Flash memory array 112 and updating RAM control registers and non-volatile erase block management registers 114. The RAM control registers and tables 114 are utilized by the control state machine 110 during operation of the Flash memory 100. The Flash memory array 112 contains a sequence of memory banks or segments 116 and one or more protection registers 128 and their associated lock bits (not shown). Each bank 116 is organized logically into a series of erase blocks (not shown). Memory access addresses are received on the address interface 104 of the Flash memory 100 and divided into a row and column address portions. On a read access the row address is latched and decoded by row decode circuit 120, which selects and activates a row page (not shown) of memory cells across a selected memory bank. The bit values encoded in the output of the selected row of memory cells are coupled from a local bitline (not shown) to a global bitline (not shown) and detected by sense amplifiers 122 associated with the memory bank. The column address of the access is latched and decoded by the column decode circuit 124. The output of the column decode circuit selects the desired column data from the sense amplifier outputs and coupled to the data buffer 126 for transfer from the memory device through the data interface 108. On a write access the row decode circuit 120 selects the row page and column decode circuit selects write circuitry 122. Data values to be written are coupled from the data buffer 126 to the write circuitry 122 selected by the column decode circuit 124 and written to the selected floating gate memory cells (not shown) of the memory array 112. The written cells are then reselected by the row and column decode circuits 120, 124 and sense amplifiers 122 so that they can be read to verify that the correct values have been programmed into the selected memory cells.
In the Flash memory 100 of FIG. 1, the protection registers 128 and the associated lock bits are included as part of the Flash memory array's 112 address map (its range of addressable memory cells), allowing the protection registers 128 and lock bits to be accessed for read and write operations utilizing column and row addresses as would the erase blocks of the Flash memory array 112. Each protection register 128 is maintained as a writeable/eraseable memory area of the Flash memory array 112 until the lock bit associated with the individual protection register or section of protection register is written, locking protection register 128 and its current data contents.
As stated above, protection registers are utilized in Flash memory devices to store security codes and/or device identifiers. There usually are 128 bits of protection register storage in a typical Flash memory device. Typically, one half of the Flash memory protection register, a 64 bit “factory” segment, is programmed and locked by the memory chip manufacturer with a device ID that identifies the Flash memory. The remaining half, the original equipment manufacturer or “OEM” segment, can be programmed and locked by the end-user or the manufacturer of a device or system that incorporates the Flash memory device. This user programmable portion of the Flash memory is typically utilized to implement security schemes, simplify manufacturing, and/or reduce system maintenance.
Examples of use of a Flash memory protection register include, but are not limited to, utilizing the protection register to store a unique number used to ensure that the application attempting to access a network is not “foreign.” Utilizing the protection register in wireless or networked devices to program a unique identifier into each unit to identify the device to the network they are a part of. Configuring a single device design to be different end-products by enabling or disabling features of the device via configuration that is stored in the protection register. Utilizing protection registers to store checksums to detect if another identifier, password, key, or section of code in the device has been modified, allowing the device to disable itself when it recognizes that it has been tampered with. The protection register can also be utilized as a check to prevent physical changes to system components by containing codes that link specific physical components or versions of components to a system. Protection registers can also be utilized to store the manufacturing or configuration information of a device in a nonvolatile, unchangeable memory space, so that, over the lifetime of a device, when the contents of the Flash memory are upgraded or reprogrammed the device model and/or overall device configuration is not lost or the device inappropriately upgraded.
A problem with protection registers and their associated lock bit(s) in Flash memories is that they are not re-programmable. This can cause issues during manufacture of the Flash memory itself as the protection register and the associated lock bit(s) may be inadvertently programmed with an erroneous device ID or code due to mistake or an organizational or marketing change. The Flash memory devices resulting from such inadvertent protection register programming would then have to be repurposed or even possibly discarded as unsuitable. Additionally, because protection registers and their associated lock bit(s) are not generally programmable they cannot be thoroughly tested and verified during manufacture of the Flash memory device. This can increase the possibility of device failure or later unsuitability for an end user trying to program the protection register and lock bit(s) due to an error or corruption in one or more bits of the protection registers or the lock bit(s). This kind of error can be due to physical damage, impurity migration, write fatigue, electrical transients, or other such reason affecting the information stored in the floating gate memory cells of protection register and lock bits.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a Flash memory device that has a protection register and associated lock bit(s) that can be reprogrammed once locked, yet be unchangeable to an eventual end user.